Altium

Design Rule Verification Report

Date:		6/30/2022
Time:		9:34:39 PM
Elapsed Time:		00:00:02
Filename:		C:\Users\Jovan\Desktop\New folder (2)\altium final\PCB.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=19.685mil) (InPolygon),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=39.37mil) (Max=78.74mil) (Preferred=39.37mil) (InNetClass('MAIN POWER'))	0
Width Constraint (Min=31.496mil) (Max=39.37mil) (Preferred=39.37mil) (InNetClass('POWER'))	0
Width Constraint (Min=31.496mil) (Max=31.496mil) (Preferred=31.496mil) (InNetClass('SIGNAL'))	0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Hole Size Constraint (Min=1mil) (Max=196.85mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=1mil) (All),(All)	0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All)	0
Silk to Silk (Clearance=0mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	0